1. Field
Exemplary embodiments of the present invention relate to a method for fabricating a semiconductor device, and more particularly, to a method for fabricating a semiconductor device with a buried word line.
2. Description of the Related Art
Pattern shrinkage may result in yield improvement. Pattern shrinkage requires a mask process that can create a smaller sized mask. In particular, ArF photoresist (PR) layers are used in semiconductor devices of not more than 40 nm. However, as the patterns are becoming finer, the ArF photoresist layers are reaching their size limitations.
Therefore, there is a demand for a new patterning technology for memory devices, such as a Dynamic Random Access Memory (DRAM), and a three-dimensional (3D) cell forming technology.
Metal Oxide Semiconductor Field Effect Transistor (MOSFET) devices with planar channels are reaching the physical limits imposed by the short channel effect, the on current, and the leakage current, thus making it difficult to further reduce the size of devices. In order to solve this problem, extensive research is being conducted on vertical-channel transistors.
A vertical-channel transistor has a channel formed in a vertical direction by forming a pillar-type active region extending vertically on a substrate, forming a gate electrode (hereinafter referred to as a vertical gate (VG)) on the sidewall of the active region, and forming junction regions such as a source region and a drain region on and under the active region with respect to the vertical gate. A buried bit line (BBL) is connected to a junction region of the vertical-channel transistor, and a storage node is connected to another junction region of the vertical-channel transistor.
FIGS. 1A to 1C are cross-sectional views illustrating a known semiconductor device. FIG. 1B is a cross-sectional view taken along a line B-B′ of FIG. 1A. FIG. 1C is a cross-sectional view taken along a line A-A′ of FIG. 1A.
Referring to FIGS. 1A to 1C, a plurality of active regions isolated by a first trench 12 are formed on a substrate 11. Each active region includes a body 13A and a pillar 13B. Each pillar 13B is formed over a respective body 13A. A hard mask layer 14 is formed on the pillar 13B. A junction 17 is formed on a portion of one sidewall of the body 13A. The first trench 12 is filled with a buried bit line 18 that is electrically connected to the junction 17. First and second liner layers 15 and 16 are formed on the sidewalls of the body 13A and the pillar 13B and the surface of the first trench 12. A word line 22 extending across the buried bit line 18 is formed on the sidewall of the pillar 13B. The pillars 13B are isolated by a second trench 23. A gate dielectric 20 is formed between the word line 22 and the pillar 13B. The word line 22 also serves as a vertical gate (VG).
In the above described technology, an etch-back process is performed to form the buried bit line 18 (hereinafter referred to as a BBL etch-back process). Also, an etching process is performed to form the word line 22 (hereinafter referred to as a VG etching process).
The BBL etch-back process and the VG etching process have no etch end point in terms of structure, and have a very large process variation. Therefore, a process variation of the two etching processes must be considered to prevent an electrical short between the buried bit line 18 and the word line 22.
For example, it is difficult to maintain the residual thickness R of an interlayer dielectric 19 as a result of the VG etching process. That is, it is difficult to control the depth of the second trench 23 created to isolate the word lines 22.
Also, the surface morphology of the buried bit line 18 is not uniform in the BBL etch-back process. Therefore, it is difficult to secure the uniformity of the word line 22 in a subsequent process.
Also, using a spacer 21 as an etch barrier, a VG etching process is performed to form the word line 22. However, it is difficult to selectively etch the hard mask layer 14 and the spacer 21 in the VG etching process. Therefore, the loss 24 of the body 13A is difficult to control, thus degrading the uniformity of the VG etching process.